1. Field of the Invention
The present invention relates to a technique for improving protecting performance with respect to electrostatic discharge (ESD) in a highly-integrated semiconductor integrated circuit.
2. Description of the Related Art
Even when the semiconductor integrated circuit is staying in the time of OFF-STATE the semiconductor integrated circuit wastes a slight leakage current (hereinafter referred to as an off leak current). It is because all the elements such as MOS (Metal Oxide Semiconductor) transistors, PN junction diodes and the like which compose the semiconductor integrated circuit have immanent off leak current. Recently, the circuit scale is increasing, to realize highly performance in the semiconductor integrated circuit. Accordingly, the off leak current of the electronic component that was incorporated the semiconductor integrated circuit is increasing. Therefore the interest to the technology that decreases the off leak current of the semiconductor integrated circuit is rising.
On the other hand, in a semiconductor integrated circuit, a function circuit for executing a predetermined function requires an ESD protection circuit for protection against ESD surge intruding from the outside. An ESD protection circuit having a guard ring is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 6-97374. Further, a so-called GGNMOS (Gate Grounded NMOS) is widely used as an ESD protection circuit.
In the case of using a GGNMOS as an ESD protection circuit, because the GGNMOS is connected in parallel to the function circuit, the whole off leak current of the semiconductor integrated circuit is the total sum of the off leak current wasted through the function circuit and that of the GGNMOS. Therefore, reducing the off leak current of the GGNMOS contributes to a reduction in the overall off leak current of the semiconductor integrated circuit. Here, the trade-off between the ESD protecting performance and the off leak current of a GGNMOS is a problem in conventional semiconductor integrated circuits. Namely, in a conventional ESD protection circuit using a GGNMOS, if an attempt is made to improve the ESD protecting performance (in particular, the responsiveness to ESD surge), the off leak current is increased unexpectedly
This point will be explained hereinafter with reference to the drawings.
FIG. 1 is a schematic diagram of a conventional semiconductor integrated circuit 8 which includes a GGNMOS. In the semiconductor integrated circuit 8 (which will hereinafter simply be called “integrated circuit 8”), the power source potential is supplied to the VDD terminal and the ground potential is supplied to the GND terminal. A line 800 (ground line) and a line 801 (power source line) are connected to the GND terminal and the VDD terminal respectively. A function circuit 10, which is for executing a predetermined function of the integrated circuit 8, and an NMOS transistor Q22 a GGNMOS are connected in parallel between the line 800 and the line 801. In FIG. 1, CMOS inverters are shown as a simple example of the internal function circuit 10. As shown in FIG. 1, an NPN-type parasitic bipolar transistor QP22 is formed under the NMOS transistor Q22 in physical structure.
The drain of the NMOS transistor Q22 (the collector of the parasitic bipolar transistor QP22) is connected to the line 801 via a node 902. The source of the NMOS transistor Q22 (the emitter of the parasitic bipolar transistor QP22) is connected to the line 800 via a node 901. The substrate of the NMOS transistor Q22 (the base of the parasitic bipolar transistor QP22) is connected to the line 800 via a substrate resistor Rs and a node 903.
A case in which an ESD event occurs at the VDD terminal of this integrated circuit 8 will be described. When a positive ESD surge is applied to the line 801 due to this ESD event, the function circuit 10 is protected due to the MOS transistor Q22 causing a breakdown. Namely, due to the rise in the substrate potential caused by the breakdown of the NMOS transistor Q22, the parasitic bipolar transistor QP22 turns on, and as shown in FIG. 1, surge current is emitted to the ground through a current path which is directed from the node 902 toward the node 901.
It is important that the breakdown of NMOS transistor Q22 occurs earlier than that of the NMOS transistors (Q101 and the like) in this ESD protection event.
However, by using the NMOS transistor Q22 composed with GGNMOS, the conventional semiconductor integrated circuit which accomplishes a large integration scale, it is difficult to keep finely the both characteristic that are a low off leak current and better ESD protection. This point will be described hereinafter.
First, the relationship between the gate length and the ESD protecting performance is shown with reference to FIG. 2. FIG. 2 is an imaginable graph showing that indicates the relationships (V-I characteristics) between the voltage of the line 801 and the current flowing to the GND terminal from the drain of the NMOS transistor Q22 when an ESD event occurs at the VDD terminal of the integrated circuit 8. As shown in FIG. 2, (a) shows a case in which the gate length of the NMOS transistor Q22 is a minimum and the gate width is sufficiently large, and (b) shows a case in which the gate length of the NMOS transistor Q22 is a minimum and the gate width is small, and (c) shows a case in which the gate length of the NMOS transistor Q22 is sufficiently large. Note that, (d) in FIG. 2 shows the V-I characteristic of the function circuit 10 for reference.
The V-I characteristics shown in FIG. 2 are generally known as snapback characteristics. In FIG. 2, in the case of (a), the NMOS transistor Q22 could taken on the surge current of 1.33 A (a current value corresponding to 2 kV HBM (Human Body Model) which is an official standard) before the function circuit 10 reaching the critical voltage (breakdown voltage). In the case of (b), it suggests that the possibility, that the function circuit reaches to breakdown voltage previously even from that the NMOS transistor Q22 pour surge current sufficiently. In the case of (c), any transistor that composes the function circuit causes the breakdown previously even from the breakdown of the NMOS transistor Q22. Therefore, there is the possibility that the function circuit 10 will receive ESD damage. As also, in the case of (c), function circuit 10 is not protected, even if the gate width is enlarged.
From the above, it can be understood that, in order to improve the ESD protecting performance of the NMOS transistor Q22 using a GGNMOS, mainly, it is necessary to make the gate length as short as possible.
On the other hand, as for the MOS transistor, it is known that a negative correlation between the off leak current and the gate length generally.
Therefore, in FIG. 2, in the case of (a), the off leak current is extremely large. In the case of (b), because the gate width is smaller than in the case of (a), the off leak current is smaller than in the case of (a). In the case of (c), because the gate length is sufficiently large, the off leak current is small.
Accordingly, as can be understood by referring to FIG. 2, in a GGNMOS (the NMOS transistor Q22), there is a trade-off between the ESD protecting performance and the off leak current. Namely, in a GGNMOS (the NMOS transistor Q22), if the gate length is made to be large, it brings both the ESD protecting performance deteriorates and the off leak current decreases. If the gate length is made to be small, it makes improvement of the ESD protecting performance and increasing of the off leak current.
The ill effects due to the trade-off between the ESD protecting performance and the off leak current of a GGNMOS become even more marked as the integration scale of the function circuit is increased. This point will be described by referring to FIG. 1 again.
In FIG. 1, in order to increase the integration scale of the function circuit 10, the gate length of the NMOS transistors within the function circuit 10 is usually designed to be the minimum value which is allowed in the fabrication process. On the other hand, in order for the NMOS transistor Q22 to attempt to cause a breakdown before the NMOS transistors within the function circuit 10 from the standpoint of ESD protection, the gate length of the NMOS transistor Q22 must be made to be shorter than the NMOS transistors within the function circuit 10. The gate length of the NMOS transistors within the function circuit 10 is the minimum value which is allowed in the fabrication process naturally, a transistor of a gate length which is shorter than that cannot be fabricated. Therefore, the gate length of the NMOS transistor Q22 is also designed to be the minimum value which is allowed in the fabricating process.
In this conventional integrated circuit 8 shown in FIG. 1, PMOS transistors (Q101, Q103, and the like) which are connected in series to the NMOS transistors become load resistances and work to delay the NMOS(Q102, Q104, and the like) breakdown timing.
In this way, even if the gate lengths of the MOS transistors in the function circuit 10 and the NMOS transistor Q22 are equal values (the minimum value allowed in the fabricating process), due to the NMOS transistor Q22 causing a breakdown earlier than the MOS transistors in the function circuit 10 and moving on to bipolar operation (the parasitic bipolar transistor QP22 turning on), the function circuit 10 is protected from an ESD event. However, the ESD protecting performance in this case relies on the existence of a PMOS transistor within the function circuit 10, and it is difficult to ensure a good ESD protecting performance by only a GGNMOS independently from the function circuit 10.
As described above, in the integrated circuit 8 which aims for a large integration scale, it is difficult to ensure a good ESD protecting performance, and in addition, when the gate length of the NMOS transistor Q22 using a GGNMOS is small, the off leak current of the NMOS transistor Q22 becomes very large. Namely, in a conventional semiconductor integrated circuit, it is difficult to keep finely the both characteristic that are a low off leak current and better ESD protection for the NMOS transistor Q22 in FIG. 1, and it has been desired to overcome this problem.